1. Field of the Invention
The invention relates in general to a bus interconnection design and, in particular, to a bus interconnection design based on transaction ID.
2. Description of the Prior Art
Advanced eXtensible Interface (abbreviated as AXI hereafter), the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which makes it very suitable for high speed sub-micrometer interconnect(ions)?. The AXI bus system supports multiple outstanding addresses issue and out of order completion and therefore needs an encoding table to identify different transactions. The conventional method is to append the ID bits, which are used to identify each master, to a transaction ID to identify which master is the source of the transaction.
FIG. 1A shows an example of using the conventional method to obtain the encoding table. There are 7 masters, M0, M1, M2, M3, M4, M5, M6 and M7, and 4 slaves, S0, S1, S2 and S3, connected through an interconnecting bus. The master ID bits of M0 are 4bxxxx, which means that the master M0 can initiate 16 transactions currently; the master ID bits of M1 are 3bxxx, which means that the master M1 can initiate 8 transactions currently; the master ID bits of M2 are 2bxx, which means that the master M2 can initiate 4 transactions currently.
Each of the master, M3, M4, M5 and M6, has zero master ID width, which means only one transaction can be initiated by each of M3, M4, M5 or M6. As the total number of masters is 7, 3 bits are needed to identify each master. The interconnection will append the 3 bits to each transaction ID to make the transaction ID unique in the interconnection bus. The transaction ID from M0 is therefore 7 bits, which includes 4 bits to identify the transactions of the M0 and 3 bits for identifying the master M0 itself. When a transaction ID returns from a slave, the interconnection will decode the transaction ID to obtain the original sourcing master.
FIG. 1B shows an example of a conventional multi-level interconnecting bus design, wherein there is an internal node that has a slave port SP and a master port MP. As the slave port SP receives transactions from 6 masters and the master M1 has the longest master ID width of 3 bits, 6 bits are needed to encode all the transactions received by the slave port SP. For slave S0, 7 bits, including 6 bits to represent all the ID transactions received by the SP and one bit to identify M0 and MP, are needed to encode all the transactions received by S0.
Some solutions have been proposed in the past to reduce the width of the transaction ID. As described in US, 20120311210, titled “System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture,” slave transaction ID width can be optimized by considering sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture, and a optimized slave transaction ID for each master to any slave is then generated by removing the don't care bits in each generated slave transaction ID based on the sparse connection information. However, the solution described in the US, 20120311210 is not guaranteed to generate an optimum transaction ID width in all cases in which the interconnections between masters and slaves and the widths of master ID(s) are varied from design to design.
Therefore, what is needed is an efficient and systematic way to generate transaction ID(s) in an interconnecting bus design to optimize the width of transaction ID.